
CHAPTER 5 CLOCK GENERATOR
User’s Manual U19678EJ1V1UD
254
5.6.5 CPU clock status transition diagram
Figure 5-15 and Figure 5-16 shows the CPU clock status transition diagram of this product.
Figure 5-15. CPU Clock Status Transition Diagram (78K0R/IC3, ID3, IE3)
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
VDD
≥ 1.61 V±0.09 V
VDD
≥ 2.7 V
VDD < 1.61 V
±0.09 V
CPU: Internal high-
speed oscillation
→ STOP
CPU: Internal high-
speed oscillation
→ HALT
CPU: X1
oscillation/EXCLK
input
→ STOP
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
CPU: Operating
with internal high-
speed oscillation
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: X1
oscillation/EXCLK
input
→ HALT
Power ON
Reset release
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
CPU:
Operating with
DSC oscillation
CPU:
DSC oscillation
→ HALT
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
DSC oscillation: Operating
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Operating
(G)
(K)
(D)
(J)
(C)
(F)
(I)
(E)
(H)
(B)
(A)
CPU:
Operating with
XT1 oscillation
CPU:
XT1 oscillation
→ HALT
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
DSC oscillation: Stops
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
Note
After reset release, operation at 4 MHz (8 MHz/2) is started, because fCLK = fIH/2 has been selected by
setting the system clock control register (CKC) to 09H.
Remark
DSC: 40 MHz internal high-speed oscillation clock