
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
511
Figure 7-99. Operation Procedure When Complementary Modulation Output Function Is Used (2/2)
Software Operation
Hardware Status
Operation
start
Sets TOE00 (master), TOEp and TOEq (slaves 2 to 7)
to 1 (only when operation is resumed).
The TS00 (master), TS01 (slave 1), TSp and TSq
(slaves 2 to 7) bits of the TS0 register are set to 1 at the
same time.
The TS00, TS01, TSp and TSq bits automatically
return to 0 because they are trigger bits.
TE00 = 1, TE01 = 1, TEp = 1, TEq = 1
When the master channel starts counting, INTTM00 is
generated. Triggered by this interrupt, the slave channels
1 also start counting.
During
operation
The set value of the TDR00 (master) register must be
changed during an up status period.
The set value of the TDRp and TDRq (slaves 2 to 7)
register can be changed.
The TCR00, TCR01, TCRp, and TCRq registers can
always be read.
Set values of the TOLp, TOLq, TROp, TROq, TMEp,
and TMEq registers can be changed.
6-Phase triangular wave PWM output is performed by the
master channel and slave channels 2 to 7.
At slave channel 1, the values of the TDR01 register are
transferred to TCR01, triggered by INTTM00 of the master
channel, and the counter starts counting down.
Slave channels 2 to 7 perform real-time output by using the
INTTM01
signal
of
slave
channel
1.
Complementary
modulation output of the PWM and real-time outputs is
performed according to setting of TMEp and TMEq.
After that, the above operation is repeated.
The TT00 (master), TT01 (slave 1), TTp, and TTq
(slaves 2 to 7) bits are set to 1 at the same time.
The TT00, TT01, TTp, and TTq bits automatically
return to 0 because they are trigger bits.
TE00, TE01, TEp, TEq = 0, and count operation stops.
TCR00 TCR01, TCRp, and TCRq hold count value and stops.
The TO00, TOp, and TOq output is not initialized but holds
current status.
Operation
stop
Sets the TOE00 (master), TOEp and TOEq (slaves 2 to
7) bits to 0, TO00, TOp, and TOq bits to value.
The TO00, TOp, and TOq pins output the TO00, TOp, and
TOq set level.
To hold the TO00, TOp, and TOq pins output level
Clears the TO00, TOp, and TOq bits to 0 after the
value to be held is set to the port register.
When holding the TO00, TOp, and TOq pins output level
is not necessary
Switches the port mode register to input mode.
The TO00, TOp, and TOq pins output level is held by port
function.
The TO00, TOp, and TOq pins output level goes into Hi-Z
output state.
TAUS
stop
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00, TOp, and TOq bits are cleared to 0 and the
TO00, TOp, and TOq pins are set to port mode.)
Remark
p = 02, 04, 06
q = 03, 05, 07
Oper
ation
is
re
su
med.