
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
390
Figure 7-18. Operation Procedure of Real-Time Output Function (Type 1) (1/2)
Software Operation
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAUS
default
setting
Sets the TPS0 register.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
[Real-time output trigger generation channel (TRCn = 1)]
Sets the TMRn register (determines operation mode
of channel).
Sets interval (period) value to the TDRn register.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets the TRCm bit to 1 (trigger generation channel).
Sets the TREm bit to 1 (real-time output enable).
The TOn and TOm pins go into Hi-Z output state.
[Real-time output channel (TRCm = 0)]
Sets the TRCm bit to 0 (non-trigger generation
channel).
Sets the TREm bit to 1 (real-time output enable).
Channel
default
setting
Sets the TOEn and TOEm bits to 1 and enables
output of TOn and TOm.
Clears the port register and port mode register to 0.
TOn and TOm do not change because channel has stopped
operating.
The TOn and TOm pins output the TOn and TOm set levels.
Operation
start
Sets the TOEn and TOEm bits to 1 (only when operation
is resumed).
Sets the TSn bit of the trigger generation channel to 1.
The TSn bit automatically returns to 0 because it is a
trigger bit.
[Real-time output trigger generation channel (TRCn = 1)]
TEn = 1, and count operation starts.
Value of TDRn is loaded to TCRn at the count clock input.
INTTMn is generated if the MDn0 bit of the TMRn register
is 1.
During
operation
Set value of the TDRn register can be changed.
The TCRn register can always be read.
Set values of the TROn and TROm bits can be
changed.
Counter (TCRn) counts down. When count value reaches
0000H, the value of TDRn is loaded to TCRn again and the
count operation is continued. By detecting TCRn = 0000H,
INTTMn is generated. After that, the above operation is
repeated.
The set value of TROm of the real-time output channel is
output from TOm at the INTTMn output timing.
The TTn bit is set to 1.
The TTn bit automatically returns to 0 because it is a
trigger bit.
TEn = 0, and count operation stops.
TCRn holds count value and stops.
The TOn output is not initialized but holds current status
and stops.
Operation
stop
The TOEn and TOEm bits are cleared to 0 and values
are set to TOn and TOm.
The set values of TOn and TOm initialize the outputs of TOn
and TOm.
Remark
n = 01 to 10, m = 02 to 11 (78K0R/IB3: n = 01 to 07, m = 02 to 07)
Operation
is
re
su
med.