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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 1/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
FEATURES
q 100ns (5 volt supply) maximum address access time
q Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
q TTL compatible inputs and output levels, three-state
bidirectional data bus
q Typical radiation performance
- Intrinsic total-dose: 30 krad(Si) nominal
- Space environment shields to >100 krad(Si)
- SEL Immune >100 MeV-cm
2/mg
- Onset LET < 1 MeV-cm2/mg
- Memory Cell Saturated Cross Section, 7.32E-8cm2/bit
- 1.5E-7 errors/bit-day, Adams 90% geosynchronous
heavy ion
- Inherent Neutron Hardness: 1.0E14n/cm2
- Nominal Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
q Packaging options:
- 32-lead ceramic flatpack
q Standard Microcircuit Drawing 5962-99606
- QML T and Q compliant
INTRODUCTION
The UT7Q512 is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E1),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power
consumption by more than 90% when deselected
.
Writing to the device is accomplished by taking the Chip
Enable One (E1) input LOW and the Write Enable (W) input
LOW. Data on the eight I/O pins (DQ0 through DQ7) is then
written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking Chip Enable One (E1) and Output Enable (G) LOW
while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified
by the address pins will appear on the eight I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected ( E1,
HIGH), the outputs are disabled (G HIGH), or during a write
operation (E1 LOW and W LOW).
Standard Products
UT7Q512 512K x 8 SRAM
Advanced Data Sheet
February 7, 2000
Figure 1. UT7Q512 SRAM Block Diagram
Memory Array
1024 Rows
512x8 Columns
Pre-Charge Circuit
Clk. Gen.
R
o
w
S
e
le
ct
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A
1
0
A
1
A
1
2
A
1
3
A
1
4
A
1
5
A
1
6
A
1
7
A
1
8
DQ 0 - DQ 7
W
G
E
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| UT7R995 | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
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| UT7R995C-XCA | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer |
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