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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 3/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
11
DATA RETENTION CHARACTERISTICS (Pre-Radiation)
(TC = 25°C, VDD = 4.5V, 10 Sec Data Retention Pulse)
Notes:
1. E1 = VSS, all other inputs = VDR or VSS.
2. Not guaranteed or tested.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
VDR
VDD for data retention
4.5
--
V
IDDR
1
Data retention current
--
.4
mA
tEFR
1,2
Chip deselect to data retention time
0
ns
tR
1,2
Operation recovery time
tAVAV
ns
VDD
DATA RETENTION MODE
tR
50%
VDR > 4.5V
Figure 5. Low VDD Data Retention Waveform (100ns)
tEFR
E1
50%
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns
2.8V
300 ohms
50pF
CMOS
0.5V
VDD-0.05V
90%
10%
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