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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 6/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
3
WRITE CYCLE
A combination of W less than VIL(max) and E1 less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when W is less
than VIL(max).
Write Cycle 1, the Write Enable-Controlled Access in figure 4a,
is defined by a write terminated by W going high, with E1 still
active. The write pulse width is defined by tWLWH when the
write is initiated by W, and by tETWH when the write is initiated
by E1. Unless the outputs have been previously placed in the
high-impedance state by G, the user must wait tWLQZ before
applying data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-Controlled A ccess in figure 4b,
is defined by a write terminated by the latter of E1 going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by W, and by tETEF when the write is initiated by the
E1going active. For the W initiated write, unless the outputs
have been previously placed in the high-impedance state
by G, the user must wait t WLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Typical Radiation Hardness
Design Specifications
1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose
30
krad(Si) nominal
Heavy Ion
Error Rate
2
1.5E-7
Errors/Bit-Day
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