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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 5/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
2
PIN NAMES
DEVICE OPERATION
The UT7Q512 has three control inputs called Enable 1 (E1),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). The E1
Device Enable controls device selection, active, and standby
modes. Asserting E1 enables the device, causes IDD to rise to its
active value, and decodes the 19 address inputs to select one of
524,288 words in the memory. W controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V IH (min), G and E1 less than
VIL (max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM read Cycle 1, the Address Access in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified tAVQV is satisfied. Outputs remain
active throughout the entire cycle. As long as Device Enable and
Output Enable are active, the address inputs may change at a
rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-Controlled Access in
figure 3b, is initiated by E1 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified tETQV is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable-Controlled Access in
figure 3c, is initiated by G going active while E1 is asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0)
Address
DQ(7:0)
Data Input/Output
E1
Chip Enable
W
Write Enable
G
Output Enable
VDD
Power
VSS
Ground
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Figure 2. 100ns SRAM Pinout (32)
VDD
A15
A17
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
G
W
E1
I/O Mode
Mode
X
1
X
1
3-state
Standby
X
0
Data in
Write
1
0
3-state
Read
2
0
1
0
Data out
Read
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