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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 12/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Q(8:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
W
tAVWL
Figure 4a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Q(7:0)
E1
tAVAV2
D(7:0)
APPLIED DATA
tDVWH
tWHDX
tETWH
tWLWH
tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
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