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参数资料
| 型号： | UT7Q512-UPA |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 100 ns, CDFP32 |
| 封装： | CERAMIC, FP-32 |
| 文件页数： | 10/12页 |
| 文件大小： | 142K |
| 代理商： | UT7Q512-UPA |
7
Assumptions:
1. E1 and G < VIL (max) and W > VIH (min)
A(18:0)
DQ(7:0)
Figure 3a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data
Valid Data
Assumptions:
1. G < VIL (max) and W > VIH (min)
A(18:0)
Figure 3b. SRAM Read Cycle 2: Chip Enable - Controlled Access
E1
DATA VALID
tEFQZ
tETQV
tETQX
DQ(7:0)
Figure 3c. SRAM Read Cycle 3: Output Enable - Controlled Access
A(18:0)
DQ(7:0)
G
tGHQZ
Assumptions:
1. E1< VIL (max) and W > VIH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
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