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| 型号： | V58C2256404SBJ5 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.65 ns, PBGA60 |
| 封装： | LEAD FREE, MO-233, FBGA-60 |
| 文件页数： | 38/62页 |
| 文件大小： | 983K |
| 代理商： | V58C2256404SBJ5 |
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43
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SB
V58C2256(804/404/164)SB Rev. 1.0 November 2003
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure D.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between
.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from
a properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3
of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than
1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. Note 42 is not used.
NOTES: (continued)
43. Note 43 is not used.
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may
be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-
sistance is used between the VTT supply and the input pin.
45. Note 45 is not used.
46. tRAP t RCD.
47. Note 47 is not used.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO
REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F
except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed
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相关代理商/技术参数 |
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