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参数资料
| 型号： | VTERB-BLK-E2-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 14/34页 |
| 文件大小： | 0K |
| 描述： | IP CORE VITERBI DECODER EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | VTERBBLKE2U4 |
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Lattice Semiconductor
Functional Description
Interfacing with the Block Viterbi Decoder
Lattice’s Block Viterbi Decoder provides several handshake signals for interfacing the decoder with other sub-sys-
tems.
In non-punctured, continuous modes, the input and output data rates are the same and it is straightforward to con-
nect the decoder in a system. The only control output in these modes, outvalid , indicates when the output data
is ready. Initially at reset, outvalid is low and it goes high after several clock cycles depending on the output
latency for the chosen configuration. The latency depends on different decoder parameters, but mainly on trace-
back length. A sample timing diagram for this configuration is shown in Figure 2-7. The hybrid version of the non-
punctured, continuous Viterbi decoder uses similar handshake mechanism as the parallel version. The main differ-
ence is that the data rate is a fraction of the clock rate for hybrid implementations. Figure 2-9 shows the timing dia-
gram for a sample hybrid decoder.
A punctured, continuous mode Viterbi decoder has an additional input signal, pbstart , which is used to specify
the start of each punctured block. This signal is required to synchronize the punctured blocks correctly for depunc-
turing inside the decoder. As in non-punctured mode, the input is assumed to be continuous. The output will have
one gap per puncture block, which is indicated by outvalid going low. This gap is required to account for the data
rate differences between the input and the output of the decoder. Figure 2-8 shows the timing diagram for a sample
punctured, continuous decoder. The hybrid mode for this implementation has similar timing characteristics, except
that the data rate is a fraction of the clock rate and hence the data and output control signals accordingly span mul-
tiple clock cycles. However the input control signals are all single clock cycle pulses as they are scanned only for
When a Viterbi Decoder is configured for block modes, the signals ibstart and ibend are used to specify the
start and end of input blocks. For fixed puncturing decoders, when the decoder is configured for zero flushing termi-
nation mode with two tracebacks, an additional output control signal rfib is provided. After an ibend signal is
applied signifying the end of a block, the next ibstart can only be applied, after the rfib goes high. To ensure
processing of blocks without discontinuity, the rfib signal goes high at the end of every L cycles, where L is the
traceback length. So if a block ends exactly at a traceback length boundary, rfib will go high while ibend goes
high, allowing ibstart to be applied in the next clock cycle. This way continuous blocks can be applied to the
decoder. For dynamic puncturing decoders, the rfib port is always present. The signal rfib goes low one cycle
after ibstart is received. It remains low during the time an input block is received. It goes high a few cycles after
ibend comes through. Refer to Figure 2-11 for a sample timing diagram for a block decoder.
When it is required to change the code rate or puncture pattern dynamically during the operation of the decoder,
the Block Viterbi Decoder can be configured as a dynamic puncturing decoder. In this mode, the code rate and
puncture patterns are set through input ports. The code rate is set using the input ports inrate and outrate .
Care should be taken to ensure the following rule is followed for the rates: inrate < outrate < 2*inrate. Other-
wise the decoder will not function correctly. An exception to this rule is when inrate = 1, at which time, the out-
rate has to be 2. Each of the puncture patterns must be inrate bits wide and the total number of ‘1’s in PP0 and
PP1 must be equal to outrate . The values of inrate , outrate , PP0 and PP1 are read-in only when ppset
goes high. The new puncture settings are set when ppset goes high and they are effective from the next input
block. Before the decoder is applied with the first block, the puncture settings have to be set. Figure 2-12 shows the
timing diagram for a typical dynamic punctured decoder.
IPUG32_02.7, June 2010
14
Block Viterbi Decoder User’s Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| VTERB-BLK-E3-U4 | 功能描述:开发软件 Block Viterbi Decoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-E3-UT4 | 功能描述:开发软件 BLOCK VITERBI DECODER (ECP3) RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-P2-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-PM-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-SC-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
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