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参数资料
| 型号： | VTERB-BLK-E2-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 26/34页 |
| 文件大小： | 0K |
| 描述： | IP CORE VITERBI DECODER EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | VTERBBLKE2U4 |
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Lattice Semiconductor
IP Core Generation
Instantiating the Core
The generated Viterbi IP core package includes black-box (< username >_bb.v) and instance (< user-name >_inst.v)
templates that can be used to instantiate the core in a top-level design. An example RTL top-level reference source
file that can be used as an instantiation template for the IP core is provided in ?
\< project_dir >\blk_vd_eval\< username >\src\rtl\top . Users may also use this top-level reference as
the starting template for the top-level for their complete design.
Running Functional Simulation
Simulation support for the Viterbi IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator, Mentor
Graphics ModelSim simulator. The functional simulation includes a configuration-specific behavioral model of the
Viterbi IP core. The test bench sources stimulus to the core, and monitors output from the core. The generated IP
core package includes the configuration-specific behavior model (< username >_beh.v) for functional simulation in
the “Project Path” root directory. The simulation scripts supporting ModelSim evaluation simulation is provided in
\< project_dir >\blk_vd_eval\< username >\sim\modelsim\scripts . The simulation script supporting
Aldec evaluation simulation is provided in ?
\< project_dir >\blk_vd_eval\< username >\sim\aldec\scripts . Both ModelSim and Aldec simulation
is supported via test bench files provided in \< project_dir >\blk_vd_eval\testbench . Models required for
simulation are provided in the corresponding \models folder. Users may run the Aldec evaluation simulation by
doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro .
3. Browse to folder \< project_dir >\blk_vd_eval\< username >\sim\aldec\scripts and execute one
of the "do" scripts shown.
Users may run the ModelSim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder ?
< project_dir >\blk_vd_eval\< username >\sim\modelsim\scripts .
3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation completes, a pop-up window will appear asking “Are you sure you want to finish?”
Answer No to analyze the results. Answering Yes closes ModelSim.
Synthesizing and Implementing the Core in a Top-Level Design
The Block Viterbi Decoder IP itself is synthesized and provided in NGO format when the core is generated through
IPexpress. You may combine the core in your own top-level design by instantiating the core in your top-level file as
described in “Instantiating the Core” on page 26 and then synthesizing the entire design with either Synplify or Pre-
cision RTL Synthesis.
The following text describes the evaluation implementation flow for Windows platforms. The flow for Linux and
UNIX platforms is described in the Readme file included with the IP core.
The top-level file < userame >_top.v is provided in ?
\< project_dir >\blk_vd_eval\< username >\src\rtl\top . Push-button implementation of the reference
design is supported via the project file < username >.ldf (Diamond) or .syn (ispLEVER) located in
\< project_dir >\blk_vd_eval\< username >\impl\(synplify or precision) .
IPUG32_02.7, June 2010
26
Block Viterbi Decoder User’s Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| VTERB-BLK-E3-U4 | 功能描述:开发软件 Block Viterbi Decoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-E3-UT4 | 功能描述:开发软件 BLOCK VITERBI DECODER (ECP3) RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-P2-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-PM-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-SC-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
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