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参数资料
| 型号： | VTERB-BLK-E2-U4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 4/34页 |
| 文件大小： | 0K |
| 描述： | IP CORE VITERBI DECODER EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | VTERBBLKE2U4 |
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Chapter 1:
Introduction
The Block Viterbi Decoder IP core is a parameterizable Viterbi Decoder for decoding different combinations of con-
volutionally encoded sequences. The decoder supports various code rates, constraint lengths, and generator poly-
nomials. It also allows soft-decision decoding and is capable of decoding punctured codes. The core can operate in
continuous or block modes, whichever is required by the channel. Either Tail Biting or Zero Flushing convolutional
codes can be decoded in the block mode. All the configurable parameters, including operation mode, generator
polynomials, punctured block size, and puncture pattern can be defined by the user to suit the needs of their appli-
cation. The code rate and puncture pattern can also be changed dynamically through input ports during the opera-
tion of the decoder. Lattice’s Block Viterbi Decoder IP is compatible with many networking and wireless standards
that use different methods of convolutional encoding at the encoder.
Quick Facts
Table 1-1 through Table 1-4 give quick facts about the Block Viterbi Decoder IP core for LatticeEC?, Lat-
ticeECP?, LatticeECP2?, LatticeECP2M?, LatticeECP3?, LattticeSC?, LatticeSCM?, LatticeXP?, and
LatticeXP2?, devices.
Table 1-1. Block Viterbi Decoder IP Core for LatticeEC/ECP/XP Devices Quick Facts
Block Viterbi IP Configuration
IEEE
802.16
2004- SC
PHY
3GPP
DVB-S
IEEE
802.11A
IEEE 802.16-
2004-OFDM
PHY
(dynamic
puncturing)
IEEE 802.16-
2004-OFDM
PHY (fixed
puncturing)
FPGA Families Supported
LatticeEC/ECP/XP
Core ?
Requirements
Minimal Device Needed
LFEC1E
LFECP6E
LFXP3C
LFEC10E
LFECP10E
LFXP10C
LFEC3E
LFECP6E
LFXP3C
LFEC3E
LFECP6E
LFXP3C
LFEC6E
LFECP6E
LFXP6C
Targeted Device
LFEC20E-5F672C/ LFECP20E-5F672C/ LFXP20E-5F256C
Resource ?
Utilization
LUTs
sysMEM EBRs
Registers
500
2
250
9950
16
3200
2600
4
900
2750
4
1050
3300
4
1200
Lattice Implementation
Diamond ? 1.0 or ispLEVER ? 8.1
Design Tool ?
Support
Synthesis
Simulation
Synopsys ? Synplify ? Pro for Lattice D-2009.12L-1
Aldec ? Active-HDL ? 8.2 Lattice Edition
Mentor Graphics ? ModelSim ? SE 6.3F
IPUG32_02.7, June 2010
4
Block Viterbi Decoder User’s Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| VTERB-BLK-E3-U4 | 功能描述:开发软件 Block Viterbi Decoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-E3-UT4 | 功能描述:开发软件 BLOCK VITERBI DECODER (ECP3) RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-P2-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| VTERB-BLK-PM-U4 | 功能描述:开发软件 Blck Viterbi Decodr User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| VTERB-BLK-SC-U4 | 功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
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