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参数资料
| 型号： | W19B320SBB9B |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | TFBGA-48 |
| 文件页数： | 2/52页 |
| 文件大小： | 1869K |
| 代理商： | W19B320SBB9B |
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W19B(L)320ST/B
- 10 -
Customer Lockable: Security Sector NOT Programmed or Protected At the Factory
If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory
space. When in system design, this issue should be considered. The Security Sector can be read,
programmed, but cannot be erased. Please note that when programming the Security Sector, the
accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector
area can be protected using one of the following procedures:
Write the three-cycle Enter Security Sector Region command sequence, and then follow the
in-system sector protect algorithm, except that #RESET may be at either VIH or VID. This
allows in-system protection of the Security Sector without raising any device pin to a high
voltage.
Please note that this method is only suitable for the Security Sector.
Write the three-cycle Enter Security Sector Region command sequence, and then use the
alternate method of sector protection described in the “Sector/ Sector Block Protection and
Unprotection” section. When the Security Sector is locked and verified, the system must write
the Exit Security Sector Region command sequence to return to reading and writing the
remainder of the array.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotecting the Security Sector area and none of the bits in the Security Sector memory space can
be modified in any ways.
6.1.13 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 nS (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
6.2 Command Definitions
The device operation can be initiated by writing specific address and data commands or sequences
into the command register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
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