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参数资料
| 型号： | W19B320SBB9B |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | TFBGA-48 |
| 文件页数： | 8/52页 |
| 文件大小： | 1869K |
| 代理商： | W19B320SBB9B |
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W19B(L)320ST/B
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DQ6 toggles. While if the device enters the Erase Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively,
the system can use DQ7 (see DQ7: #Data Polling).
If a program address falls within a protected sector, DQ6 toggles for about 1
s after the program
command sequence is written, and then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling when the Embedded
Program algorithm is complete.
Please also refer to DQ2: Toggle Bit II.
6.3.4 DQ2: Toggle Bit II
When used with DQ6, the “Toggle Bit II” on DQ2 indicates whether a particular sector is actively
erasing (i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final #WE pulse in the command sequence.
DQ2 toggles as the system reads at addresses within those sectors that have been selected for
erasure. (The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot
distinguish that whether the sector is actively erasing or is erase-suspended. By comparison, DQ6
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Therefore, both status bits are required for sector and mode
information.
6.3.5 Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0
DQ7 at least twice in a
row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the
value of the toggle bit after the first read. While after the second read, the system would compare the
new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ0
DQ7 on the following read
cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is
high, the system should then determine again whether the toggle bit is toggling or not, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not
completed the operation, and the system must write the reset command to return to reading array
data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5 through successive read cycles, and
determines the status as described in the previous paragraph. Alternatively, the system may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
while it returns to determine the status of the operation.
6.3.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
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