
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-56 -
8.1.17 D_ch TEI2 Register D_TEI2
Read/Write
Address 40H/10H
Value after reset: 00H
7
6
5
4
3
2
1
0
TA27
TA26
TA25
TA24
TA23
TA22
TA21
TA20
TA27 - TA20
This register contains the second choice of the second byte address of received frame. For LAPD frame, TA27 - TA21 is the
TEI value, TA20 is EA = 1.
8.1.18 D_ch Receive Frame Byte Count High
D_RBCH
Read Address 44H/11H
Value after reset: 40H
7
6
5
4
3
2
1
0
VN1
VN0
LOV
RBC12
RBC11
RBC10
RBC9
RBC8
VN1-0
Chip Version Number
This is the chip version number. It is read as 01B.
LOV
Length Overflow
A "1" in this bit indicates
≥ 8192 bytes are received and the frame is not yet complete. This bit is valid only after an D_RME
interrupt and remains valid until the frame is acknowledge via the RACK command.
RBC12-8
Receive Byte Count
Four most significant bits of the total frame length. These bits are valid only after an D_RME interrupt and remain valid until the
frame is acknowledge via the RACK command.
8.1.19 D_ch Receive Frame Byte Count Low
D_RBCL
Read
Address 48H/12H
Value after reset: 00H
7
6
5
4
3
2
1
0
RBC7
RBC6
RBC5
RBC4
RBC3
RBC2
RBC1
RBC0
RBC7-0
Receive Byte Count
Eight least significant bits of the total frame length. Bits RBC5-0 also indicate the length of the data currently available in
D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK
command.