
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-67 -
MER1
Monitor channel 1 End of Reception
MDA1
Monitor channel 1 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
MAB1
Monitor channel 1 Data Abort
8.1.39 Monitor Channel 1 Control Register
MO1C
Read/Write
Address 79H/43H
Value after reset: 00H
7
6
5
4
3
2
1
0
MRIE1
MRC1
MXIE1
MXC1
MRIE1
Monitor Channel 1 Receive Interrupt Enable
Monitor channel interrupt status MDR1, MER1 generation is enabled (1) or masked (0).
MRC1
MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR1 interrupt is blocked, except for the first byte of a packet (if MRE=1).
1: MR internally controlled by the W6692A according to Monitor channel protocol. In addition,
the MDR1 interrupt is
enabled for all received bytes according to the Monitor channel protocol (if MRE=1).
MXIE1
Monitor channel 1 Transmit Interrupt Enable
Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0).
MXC1
MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W6692A according to Monitor channel protocol.
8.1.40 GCI IC1 Receive Register
IC1R
Read
Address 6EH/44H
Value after reset: Undifined
7
6
5
4
3
2
1
0
Bit 7-0
Receive data of GCI IC1 channel.
8.1.41 GCI IC1 Transmit Register
IC1X
Read/Write
Address 72H/45H
Value after reset: FFH
7
6
5
4
3
2
1
0