
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-71 -
A4/29 R/W
B1_ADR1
RA17
RA16
RA15
RA14
RA13
RA12
RA11
RA10
A8/2A R/W
B1_ADR2
RA27
RA26
RA25
RA24
RA23
RA22
RA21
RA20
AC/2B R
B1_RBCL
RBC7
RBC6
RBC5
RBC4
RBC3
RBC2
RBC1
RBC0
B0/2C R
B1_RBCH
LOV
RBC12
RBC11
RBC10
RBC9
RBC8
B4/2D R/W
B1_IDLE
IDLE7
IDLE6
IDLE5
IDLE4
IDLE3
IDLE2
IDLE1
IDLE0
8.2.1 B1_ch receive FIFO
B1_RFIFO
Read
Address 80H/20H
The B1_RFIFO is a 128-byte depth FIFO memory with programmable threshold. The threshold value determines when to
generate an interrupt.
When more than a threshold length of data has been received, a RMR interrupt is generated. After an RMR interrupt, 64 or
96 bytes can be read out, depending on the threshold setting.
In transparent mode, when the end of frame has been received, a RME interrupt is generated. After an RME interrupt, the
number of bytes available is less than or equal to the threshold value.
8.2.2 B1_ch transmit FIFO
B1_XFIFO
Write
Address 84H/21H
The B1_XFIFO is a 128-byte depth FIFO with programmable threshold value. The threshold setting is the same as
B1_RFIFO.
When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt is generated. After a
XFR interrupt, up to 64 or 96 bytes of data can be written into this FIFO for transmission.
8.2.3 B1_ch command register
B1_CMDR
Read/Write
Address 88H/22H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK
RRST
RACT
XACTB B1_128
K
XMS
XME
XRST
RACK
Receive Message Acknowledge
After a RMR or RME interrupt, the microprocessor reads out the data in B1_RFIFO, it then sets this bit to explicitly
acknowledge the interrupt.
This bit is write only. It's auto-clear.
RRST
Receiver Reset
Setting this bit resets the B1_ch HDLC receiver.
This bit is write-only. It's auto-clear.
RACT
Receiver Active
"1": transmitter is active, 64 kHz clock is provided.
"0": transmitter is inactive, clock is LOW to save power.