
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-80 -
Vendor ID is Winbond
′s vendor ID: 1050
H , if EEPROM is empty.
8.4.2 Status/Command Register
Read/Write
Address 04H
PCI Configuration Address: 04H
Default: 0210 0000 H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DPE
--
STA
DEVSEL
--
FBT
UDF
66M
CAP
--
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
--
PEE
--
MAE
IOAE
Bits 31-16 are Status register and bits 15-0 are Command register. Reads to Status register behave normally. Bits in Status
register are cleared if the corresponding write data bits are '1' in a write operation.
Bits 15-0 are Command register. When 00H
is written to this register, the device is logically disconnected from the PCI bus
for all accesses except configuration accesses. The power up value of Command register is 00 H
.
Bit 31
DPE
Detected Parity Error
R/W_clr
1 = A parity error is detected.
0 = No parity error is detected.
Bit 30
SSE
Signaled System Error
Not implemented. Read as 0.
Bits 29-28
Master Aborted, Target Aborted
Not implemented. Read as 0.
Bit 27
STA
Signaled Target Abort
R/W_clr
1 = Target Abort is signaled.
0 = Target Abort is not signaled.
Bits 26-25
DEVSEL Timing
Read_only
01 = Medium DEVSEL# timing.
Bits 24
PERR# Asserted
Not implemented. Read as 0.
Bit 23
FBT
Fast Back-to-back Transaction
Read_only
0 = Unable to accept fast back-to-back transaction.
Bit 22
UDF
User Definable Features
Read_only
0 = Unable to support User Definable Features.