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参数资料
| 型号： | W948D2FBJX5E |
| 厂商： | Winbond Electronics |
| 文件页数： | 1/60页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR SDRAM 256MBIT 90VFBGA |
| 标准包装： | 240 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR SDRAM |
| 存储容量： | 256M（8Mx32） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 90-TFBGA |
| 供应商设备封装： | 90-VFBGA（8x13） |
| 包装： | 托盘 |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION .................................................................................................. 4
2. FEATURES.......................................................................................................................... 4
3. PIN CONFIGURATION ........................................................................................................ 5
3.1 Ball Assignment: LPDDR x16 ..................................................................................................... 5
3.2 Ball Assignment: LPDDR x32 ..................................................................................................... 5
4. PIN DESCRIPTION ............................................................................................................. 6
4.1 Signal Descriptions ..................................................................................................................... 6
4.2 Addressing Table ........................................................................................................................ 7
5. BLOCK DIAGRAM .............................................................................................................. 8
5.1 Block Diagram ............................................................................................................................ 8
5.2 Simplified State Diagram ............................................................................................................ 9
6. FUNCTION DESCRIPTION ............................................................................................... 10
6.1 Initialization ............................................................................................................................... 10
6.1.1 Initialization Flow Diagram ............................................................................................................. 11
6.1.2 Initialization Waveform Sequence ................................................................................................. 12
6.2 Register Definition .................................................................................................................... 12
6.2.1 Mode Register Set Operation ........................................................................................................ 12
6.2.2 Mode Register Definition ............................................................................................................... 13
6.2.3. Burst Length ................................................................................................................................. 13
6.3 Burst Definition ......................................................................................................................... 14
6.4 Burst Type ................................................................................................................................ 15
6.5 Read Latency............................................................................................................................ 15
6.6 Extended Mode Register Description ....................................................................................... 15
6.6.1 Extended Mode Register Definition ............................................................................................... 16
6.7 Status Register Read ................................................................................................................ 16
6.7.1 SRR Register (A[n:0] = 0) .............................................................................................................. 17
6.7.2 Status Register Read Timing Diagram .......................................................................................... 18
6.8 Partial Array Self Refresh ......................................................................................................... 19
6.9 Automatic Temperature Compensated Self Refresh ................................................................ 19
6.10 Output Drive Strength ............................................................................................................. 19
6.11 Commands ............................................................................................................................. 19
6.11.1 Basic Timing Parameters for Commands .................................................................................... 19
6.11.2 Truth Table - Commands ............................................................................................................. 20
6.11.3 Truth Table - DM Operations ....................................................................................................... 21
6.11.4 Truth Table - CKE ........................................................................................................................ 21
6.11.5 Truth Table - Current State BANKn - Command to BANKn ........................................................ 22
6.11.6 Truth Table - Current State BANKn, Command to BANKn ......................................................... 23
7. OPERATION...................................................................................................................... 24
7.1. Deselect ................................................................................................................................... 24
7.2. No Operation ........................................................................................................................... 24
7.2.1 NOP Command ............................................................................................................................. 25
7.3 Mode Register Set .................................................................................................................... 25
Publication Release Date : Oct, 15, 2012
-1-
Revision : A01-004
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W948D2FBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ |
| W948D2FBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ, INDUST |
| W948D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics 功能描述:LOW POWER DRAM 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 166MHZ, 65NM |
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