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| 型号： | W948D2FBJX5E |
| 厂商： | Winbond Electronics |
| 文件页数： | 45/60页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR SDRAM 256MBIT 90VFBGA |
| 标准包装： | 240 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR SDRAM |
| 存储容量： | 256M（8Mx32） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 90-TFBGA |
| 供应商设备封装： | 90-VFBGA（8x13） |
| 包装： | 托盘 |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.14 Clock Stop
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions:
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?
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the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access
command d epends on the device?s AC timing parameters and the clock frequency;
the related timing conditions (t RCD , t WR , t RP , t RFC , t MRD ) has been met;
CKE is held High
When all conditions have been met, the device is either in “idle state” or “row active state” and clock stop mode
may be entered with CK held Low and CK held High.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next
access command may be applied. Additional clock pulses might be required depending on the system
characteristics.
The following Figure shows clock stop mode entry and exit.
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Initially the device is in clock stop mode
The clock is restarted with the rising edge of T0 and a NOP on the command inputs
With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for
clock stop as soon as this access command is completed
Tn is the last clock pulse required by the access command latched with T1
The clock can be stopped after Tn
7.14.1 Clock Stop Mode Entry and Exit
T0
T1
T2
Tn
CK
CK
CKE
Timing
Condition
Command
NOP
CMD
NOP
NOP
NOP
Address
DQ,DQS
Valid
(High-Z)
= Don't Care
Clock
Stopped
Exit Clock
Stop
Mode
Valid
Command
Enter Clock
Stop Mode
Publication Release Date : Oct, 15, 2012
- 45 -
Revision : A01-004
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W948D2FBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ |
| W948D2FBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 200MHZ, INDUST |
| W948D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA 制造商:Winbond Electronics 功能描述:LOW POWER DRAM 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W948D2FBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X32, 166MHZ, 65NM |
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