- 您现在的位置：买卖IC网 > Datasheet目录369 > W949D2CBJX5E (Winbond Electronics)IC LPDDR SDRAM 512MBIT 90VFBGA Datasheet资料下载
参数资料
| 型号： | W949D2CBJX5E |
| 厂商： | Winbond Electronics |
| 文件页数： | 1/60页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR SDRAM 512MBIT 90VFBGA |
| 标准包装： | 240 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR SDRAM |
| 存储容量： | 512M（16M x 32） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 90-TFBGA |
| 供应商设备封装： | 90-VFBGA（8x13） |
| 包装： | 托盘 |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
W949D6CB / W949D2CB
512Mb Mobile LPDDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ................................................................................................. 4
2. FEATURES ......................................................................................................................... 4
3. PIN CONFIGURATION ....................................................................................................... 5
3.1 Ball Assignment: LPDDR X16 .................................................................................................. 5
3.2 Ball Assignment: LPDDR X32 .................................................................................................. 5
4. PIN DESCRIPTION ............................................................................................................. 6
4.1 Signal Descriptions................................................................................................................... 6
4.2 Addressing Table ..................................................................................................................... 7
5. BLOCK DIAGRAM.............................................................................................................. 8
5.1 Block Diagram .......................................................................................................................... 8
5.2 Simplified State Diagram .......................................................................................................... 9
6. FUNCTION DESCRIPTION ...............................................................................................10
6.1 Initialization ............................................................................................................................ 10
6.1.1 Initialization Flow Diagram ............................................................................................................. 11
6.1.2 Initialization Waveform Sequence .................................................................................................. 12
6.2 Register Definition .................................................................................................................. 12
6.2.1 Mode Register Set Operation ......................................................................................................... 12
6.2.2 Mode Register Definition ................................................................................................................ 13
6.2.3. Burst Length .................................................................................................................................. 13
6.3 Burst Definition ....................................................................................................................... 14
6.4 Burst Type .............................................................................................................................. 15
6.5 Read Latency ......................................................................................................................... 15
6.6 Extended Mode Register Description ..................................................................................... 15
6.6.1 Extended Mode Register Definition ................................................................................................ 16
6.7 Status Register Read ............................................................................................................. 16
6.7.1 SRR Register (A[n:0] = 0) .............................................................................................................. 17
6.7.2 Status Register Read Timing Diagram ........................................................................................... 18
6.8 Partial Array Self Refresh ....................................................................................................... 19
6.9 Automatic Temperature Compensated Self Refresh ............................................................... 19
6.10 Output Drive Strength ........................................................................................................... 19
6.11 Commands ........................................................................................................................... 19
6.11.1 Basic Timing Parameters for Commands .................................................................................... 19
6.11.2 Truth Table - Commands ............................................................................................................. 20
6.11.3 Truth Table - DM Operations ....................................................................................................... 21
6.11.4 Truth Table - CKE ........................................................................................................................ 21
6.11.5 Truth Table - Current State BANKn - Command to BANKn......................................................... 22
6.11.6 Truth Table - Current State BANKn, Command to BANKn .......................................................... 23
7. OPERATION ......................................................................................................................24
7.1. Deselect ................................................................................................................................ 24
7.2. No Operation ......................................................................................................................... 24
7.2.1 NOP Command .............................................................................................................................. 25
Publication Release Date: Sep, 21, 2011
-1-
Revision A01-007
相关PDF资料 |
PDF描述 |
|---|---|
| W971GG6JB25I | IC DDR2 SDRAM 1GBIT 84WBGA |
| W971GG8JB-25 | IC DDR2 SDRAM 1GBIT 60WBGA |
| W9725G6IB-25 | IC DDR2-800 SDRAM 256MB 84-WBGA |
| W9725G6JB25I | IC DDR2 SDRAM 256MBIT 84WBGA |
| W9725G6KB-25I | IC DDR2 SDRAM 256MBIT 84WBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
| W949D2CBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ, 65NM |
发布紧急采购，3分钟左右您将得到回复。