参数资料
型号: W9864G6EB-7
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA60
封装: 0.65 MM PITCH, ROHS COMPLIANT, VFBGA-60
文件页数: 9/47页
文件大小: 1136K
代理商: W9864G6EB-7
W986416EB/W9864G6EB
Publication Release Date: Sep. 23, 2005
- 17 -
Revision P06
Notes:
1. Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of Tck
and Trc.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the “NOP” state. The
CLK signals must be started at the same time.
(3) After power-up a pause of at least 200 μseconds is required. It is required that DQM and CKE signals then be
held ’high‘ (VCC levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER
CONDITIONS
Output Reference Level
1.4V
Output Load
See diagram below
Input Signal Levels (VIH/VIL)
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
1 Ns
Input Reference Level
1.4V
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
30pF
1. Transition times are measured between VIH and VIL.
2. Thz defines the time at which the outputs achieve the open circuit condition and is not referenced to output
level.
3. These parameters account for the number of clock cycles and depend on the operating frequency of the
clock, as follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
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