参数资料
型号: WED9LAPC2C16V8BC
厂商: WHITE ELECTRONIC DESIGNS CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA192
封装: 21 X 21 MM, BGA-192
文件页数: 2/24页
文件大小: 933K
代理商: WED9LAPC2C16V8BC
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Current State
Command
Action
Notes
VCRAS# VCCAS#
VCWE#
VCBS
VCADDR
Description
Refreshing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
L
X
Burst Termination
No Operation; Idle after tRC
H
X
No Operation
No Operation; Idle after tRC
Mode Register
Accessing
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
L
X
Burst Termination
ILLEGAL
H
X
No Operation
No Operation; Idle after two clock cycles
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Notes:
1.
Both Banks must be idle otherwise it is an illegal action.
2.
The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State
then the action may be legal depending on the state of that bank.
3.
The minimum and maximum Active time (tRAS) must be satised.
4.
The VCRAS# to VCCAS# Delay (tRCD) must occur before the command is given.
5.
Address VCADDR9/AP is used to determine if the Auto Precharge function is activated.
6.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (tRRD) is not
satised.
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