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| 型号： | WJLXT384LEB1 |
| 厂商： | INTEL CORP |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封装： | 20 X 20MM, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 110/140页 |
| 文件大小： | 1514K |
| 代理商： | WJLXT384LEB1 |
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71
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
7.4
Host Processor Modes
When the MODE pin is connected high, the following Host Processor modes are available.
7.4.1
Host Processor Mode - Parallel Interface
The parallel interface (listed in Table 3 in Section 4.1, “Operating Mode Multi-Function Pins”) is
used to control configuration of the LXT384 Transceiver and to report the status of various
operations. The LXT384 Transceiver has a flexible, generic 8-bit parallel host processor interface
designed to support both non-multiplexed and multiplexed address/data bus systems for both
Motorola bus and Intel
bus topologies. Table 24 lists the four parallel interface modes that can be
selected with the pins MODE, MOT/INTL, and MUX.
The Host Processor mode parallel interface includes an address bus (A4:0) and a data bus (D7:0)
for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. The
LXT384 Transceiver has a 5-bit address bus and provides 22 user-accessible 8-bit registers for
configuration, alarm monitoring, and control of the LXT384 Transceiver.
Control signals that the LXT384 Transceiver and host processors have in common include ACK/
RDY, ALE, CS, DS, INT, RD, R/W, and WR. An internal wait-state generator controls the ACK/
RDY handshake output signal, which is compatible with both Motorola and Intel processors.
When the processor interface selected is for a:
Motorola processor and ACK is low, then during a:
— Read cycle, ACK indicates that valid information is on the data bus.
— Write cycle, ACK indicates the LXT384 Transceiver has accepted the write data from the
Motorola processor.
Intel processor and RDY is:
— Low, the LXT384 Transceiver indicates to the Intel processor a bus cycle is in progress.
Note:
When an Intel
processor is used with a non-multiplexed interface, there is one exception to how
write-cycle timing operates that involves the use of Register 0Ah, the reset register. At the start of
the write cycle, the RDY line remains high instead of signaling the completion of the write cycle
with a transition to a low state. The overall duration of the reset cycle from when the signal on CS
is low to the completion of the reset cycle is a total of 3 microseconds. As a result, upon writing to
Register 0Ah, allow a minimum of 2 microseconds of constant throughput delay before attempting
the next read/write operation. (For more information on the reset cycle, see Table 38 in Section 8.3,
Table 24. Host Processor Mode - Parallel Interface Selections
MODE
MOT/
INTL
MUX
Interface Selected
High
Low
Host Processor mode, Motorola processor parallel interface, non-multiplexed
High
Low
High
Host Processor mode, Motorola processor parallel interface, multiplexed
High
Low
Host Processor mode, Intel processor parallel interface, non-multiplexed
High
Host Processor mode, Intel
processor parallel interface, multiplexed
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