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参数资料
型号： WJLXT384LEB1
厂商： INTEL CORP
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 123/140页
文件大小： 1514K
代理商： WJLXT384LEB1
83
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 43. Global Control Register, GCR - 0Fh
Bit
Name
Description
R/W
7
-
Reserved.
R/W
6
RAISEN
Receive Alarm Indication Signal Enable.
This bit controls automatic AIS insertion in the receive path when LOS occurs.
0 = Receive path AIS insertion is disabled on LOS.
1 = Receive path AIS insertion is enabled on LOS, and the effective output
appears on RPOS/RNEG.
NOTE: This feature is not available in data-recovery mode (that is, when
MCLK is high). When changing the value of the RAISEN bit, disable
AIS interrupts to prevent inadvertent interrupts.
R/W
5
CDIS
Circuit Disable.
This bit enables/disables the short-circuit protection feature for the transmitters.
0 = Enable
1 = Disable
R/W
4CODEN
Code Enable.
This bit selects one of two available zero-suppression codes. Zero suppression
operations are available only with unipolar I/O.
0 = High-Density Bipolar three (HDB3) for E1 or B8ZS for T1
1 = Alternate Mark Inversion, or ‘AMI’. The following figure shows AMI
coding that is 1:1 (or ‘50%’), indicating that for every one bit sit to a ‘1’,
there is a corresponding ‘0’ logic state.
R/W
3FIFO64
First-In First-Out 64-Bit Select.
This bit determines the jitter attenuator FIFO depth as follows:
0 = Jitter attenuator FIFO is 32 bits deep.
1 = Jitter attenuator FIFO is 64 bits deep.
R/W
2JACF
Jitter Attenuator Corner Frequency.
This bit determines the jitter attenuator low-limit 3-dB corner frequency. For
more information, see Chapter 14.0, “Jitter Performance”.
R/W
1:0
JASEL1:0
Jitter Attenuator Select.
These bits determine the jitter attenuator position as follows:
R/W
1. On power-on reset, the register is set to ‘0’.
TTIP
TRING
1
0
1
Bit Cell
JASEL1
JASEL0
Jitter Attenuator Position
x
0
Jitter attenuator is disabled.
0
1
Jitter attenuator position is the transmit path.
1
Jitter attenuator position is the receive path.
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