4
Datasheet
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Contents
6.6
Jitter Attenuation ................................................................................................. 60
6.7
Loopbacks ........................................................................................................... 62
6.7.1
Analog Loopback ................................................................................... 62
6.7.2
Digital Loopback..................................................................................... 63
6.7.3
Remote Loopback .................................................................................. 64
6.8
Transmit All Ones Operations ............................................................................. 65
6.8.1
TAOS Generation................................................................................... 65
6.8.2
TAOS Generation with Analog Loopback .............................................. 66
6.8.3
TAOS Generation with Digital Loopback................................................ 66
6.9
Performance Monitoring ...................................................................................... 67
6.10
Intel
Hitless Protection Switching ......................................................................68
7.0
Operating Mode Summary ................................................................................... 69
7.1
Interfacing with 5V Logic ..................................................................................... 69
7.2
Hardware Mode................................................................................................... 69
7.3
Hardware Mode Settings..................................................................................... 70
7.4
Host Processor Modes ........................................................................................ 71
7.4.1
Host Processor Mode - Parallel Interface............................................... 71
7.4.2
Host Processor Mode - Serial Interface ................................................. 73
7.5
Interrupt Handling................................................................................................ 74
7.5.1
Interrupt Sources.................................................................................... 74
7.5.2
Interrupt Enable...................................................................................... 74
7.5.3
Interrupt Clear ........................................................................................ 74
8.0
Registers...................................................................................................................... 75
8.1
Register Summary .............................................................................................. 75
8.2
Register Addresses ............................................................................................. 77
8.3
Register Descriptions .......................................................................................... 78
9.0
JTAG Boundary Scan............................................................................................. 86
9.1
Overview ............................................................................................................. 86
9.2
Architecture ......................................................................................................... 86
9.3
TAP Controller..................................................................................................... 87
9.4
JTAG Register Description.................................................................................. 89
9.4.1
Boundary Scan Register (BSR).............................................................. 89
9.4.2
Analog Port Scan Register (ASR) .......................................................... 94
9.4.3
Device Identification Register (IDR) ....................................................... 94
9.4.4
Bypass Register (BYR) .......................................................................... 94
9.4.5
Instruction Register (IR) ......................................................................... 95
10.0
Electrical Characteristics...................................................................................... 96
11.0
Timing Characteristics......................................................................................... 105
11.1
Intel
LXT384 Transceiver Timing ....................................................................106
11.2
Host Processor Mode - Parallel Interface Timing.............................................. 109
11.2.1 Intel
Processor - Parallel Interface Timing ......................................... 109
11.2.2 Motorola* Processor - Parallel Interface Timing................................... 115
11.3
Host Processor Mode - Serial Interface Timing ................................................ 121