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参数资料
型号： WJLXT384LEB1
厂商： INTEL CORP
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封装： 20 X 20MM, ROHS COMPLIANT, LQFP-144
文件页数： 73/140页
文件大小： 1514K
代理商： WJLXT384LEB1
38
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
MCLK
10
E1
DI
Master Clock Input.
MCLK is an independent, free-running reference clock that must be
used at 1.544 MHz for T1 operation or 2.048 MHz for E1 operation, to
generate the following internal reference signals:
Reference clock during a blue-alarm transmit-all-ones condition.
Generation of RCLK signal during a loss-of-signal condition.
Timing reference for the integrated clock-recovery unit, and the
integrated digital jitter attenuator.
Wait-state generation logic for host processors that use parallel
interfaces.
If MCLK is:
Low continuously, the complete receive path is powered down and
output pins RCLK, RPOS, and RNEG are switched to a high-
impedance tristate.
High continuously, the phase-locked loop clock-recovery circuit is
disabled and the LXT384 Transceiver operates as only a simple
data receiver (without clock recovery).
NOTE:
MCLK is not required if the LXT384 Transceiver is used as an
analog front end without clock recovery and jitter attenuation.
The TAOS generator uses MCLK as a timing reference. To ensure
the output frequency is within specification limits, MCLK must
have the applicable stability.
If MCLK is not provided, the LXT384 Transceiver cannot be used
for data recovery with Motorola processors because wait states
cannot be added. (Wait-state generation through ACK is not
available.)
Caution: Whenever MCLK is not provided, the LXT384 Transceiver is
forced into a static state, possibly causing the TTIP/TRING
outputs to overheat. To prevent overheating, see Section
6.5, “Line-Interface Protection”.
RCLK
Receive Clock Output 7:0.
For information on RCLK, see Section 5.3, “Framer/Mapper Signals”.
SCLK
Shift Clock Input.
For information on SCLK, see Section 5.2, “Microprocessor-Standard
Bus and Interface Signals”.
TCLK
Transmit Clock Input 7:0.
For information on TCLK, see Section 5.3, “Framer/Mapper Signals”.
Table 11. Clocks and Clock-Related Signals (Sheet 2 of 2)
Signal
Name
QFP
Pin
PBGA
Ball
Signal
Type
Signal Description
1. DI: Digital Input
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