参数资料
型号: WJLXT907ALCA4
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 13/48页
文件大小: 621K
代理商: WJLXT907ALCA4
Intel
LXT901A/907A Universal 3.3 V Ethernet Transceiver
20
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
magnetics and part numbers is available in Application Note 73, Magnetic Manufacturers (248991-
001), which can be found on the Intel web site (developer.intel.com/design/network/). Designers
must test and validate all components for suitability in their applications.
3.4
Typical Applications
Figure 9 on page 21 through Figure 16 on page 28 show typical LXT901A/907A Transceiver
applications.
3.4.1
Auto Port Select with External Loopback Control
Figure 9 on page 21 is a typical LXT901A/907A Transceiver application. The diagram groups
similar pins together, but does not represent the actual LXT901A/907A Transceiver pinout. The
controller interface pins (transmit data, clock and enable; receive data and clock; and the collision
detect, carrier detect and loopback control pins) are shown at the top left of the diagram.
Programmable option pins are grouped at the center left of the diagram. The PAUI pin is tied Low
and all other option pins are tied High. This setup selects the following options:
Automatic Port Selection
(PAUI Low and AUTOSEL High)
Normal Receive Threshold (NTH High)
Mode 4, compatible with National NS8390 controllers (MD0 High, MD1 High)
SQE Disabled (DSQE High for LXT907A Transceiver only)
UTP is selected (STP High for LXT901A Transceiver only)
Link Testing Enabled (LI High)
Status outputs are grouped at the lower left of the diagram. Local status outputs drive LED
indicators.
Power and ground pins are shown at the bottom of the diagram. A single power supply is used for
both VCC1 and VCC2, with a decoupling capacitor installed between the power and ground
busses. An additional power and ground pin (VCCA and GNDA) is supported in designs using the
64-pin LQFP package. A single power supply is used for all three power and ground pins (VCC1,
VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling capacitor between each power
and ground buss.
The twisted-pair and AUI interfaces are shown at the upper and lower right of the diagram,
respectively. Impedance matching resistors for 100
Ω UTP are installed in each I/O pair and no
external filters are required.
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