参数资料
型号: WJLXT907ALCA4
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 21/48页
文件大小: 621K
代理商: WJLXT907ALCA4
Intel
LXT901A/907A Universal 3.3 V Ethernet Transceiver
28
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
3.4.7
150
Ω Shielded Twisted-Pair Only (LXT901A Transceiver only)
Figure 16 shows the LXT901A Transceiver in a typical twisted-pair only application. The DTE is
connected to a 10BASE-T network through the twisted-pair RJ-45 connector. Note that the AUI
port is not used. With MD0 tied High and MD1 Low, the LXT901A Transceiver logic and framing
are set to Mode 2 (compatible with Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left
open). The L1 pin externally controls the link test function. The STP and NTH pins are both tied
Low, selecting the reduced receiver threshold and 150
Ω termination for shielded twisted-pair
cable. The switch at LEDT/PDN manually controls the power down mode.
Figure 16. 150
Ω Shielded Twisted-Pair Only Application (LXT901A Transceiver )
LX
T
901
A
TPIN
75
Ω
75
Ω
TPIP
1 : 1
116
14
6
5
4
3
2
1
11
0.1
μF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To
1
0
B
A
S
E
-T
TW
IS
TE
D
-
P
A
IR
N
E
T
W
O
R
K
RBIAS
GND2
GND1
PAUI
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
1 : 2
TEST
75
Ω 1%
37.5
Ω 1%
12.4 k
Ω 1%
2
20 MHz
SYSTEM
CLOCK
82596
BACK-END/
CONTROLLER
INTERFACE
CLK0
RCLK
75
Ω 1%
37.5
Ω 1%
+3.3 V
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
1
10K
LINE STATUS
10K
Link Test Enable
PROGRAMMING
OPTIONS
STP
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
CLK1
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
Left Open
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
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