参数资料
型号: X40411S8I-C
元件分类: 电源管理
英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封装: PLASTIC, SOIC-8
文件页数: 21/25页
文件大小: 532K
代理商: X40411S8I-C
X40410/X40411/X40414/X40415
Characteristics subject to change without notice.
5 of 25
REV 1.3.6 2/11/04
www.xicor.com
Setting a Lower VTRIPx Voltage (x=1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must rst be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1 and 0Bh for VTRIP2, followed by 00h for the
Data Byte in order to reset VTRIPx. The STOP bit fol-
lowing a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of VTRIPx becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modied by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40410/
11/14/15 will not acknowledge any data bytes written
after the rst byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus proto-
col, but a stop is not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
76
543
21
0
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
Figure 4. Sample VTRIP Reset Circuit
1
3
2
4
8
7
6
5
SOIC
VTRIP1
Adj.
VP
RESET
4.7K
SDA
SCL
C
Adjust
Run
V2FAIL
VTRIP2
Adj.
X4041x
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