参数资料
型号: X40411S8I-C
元件分类: 电源管理
英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封装: PLASTIC, SOIC-8
文件页数: 4/25页
文件大小: 532K
代理商: X40411S8I-C
X40410/X40411/X40414/X40415
Characteristics subject to change without notice.
12 of 25
REV 1.3.6 2/11/04
www.xicor.com
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The rst Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000H and the device continues to out-
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FFhex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FFhex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
General Purpose Memory Array Conguration
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
–a device type identier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
–next two bits are ‘0’.
–next bit that becomes the MSB of the address.
Figure 13. X40410/11 Addressing
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
General Purpose Memory
Control Register
Fault Detection Register
1
0
1
0
1
A8 R/W
Word Address
Slave Byte
1
0
10
1
0
R/W
General Purpose Memory
Control Register
Fault Detection Register
A7
1
A6 A5
A4
A1
A0
1
A3 A2
1
Figure 14. Current Address Read Sequence
.
S
t
a
r
t
S
t
o
p
Slave
Address
Data
SDA Bus
Signals from
the Slave
Signals from
the Master
1
10 10
0
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