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参数资料
型号： XC2S50E-6FTG256I
厂商： Xilinx Inc
文件页数： 29/108页
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 50K 256FTBGA
产品变化通告： FPGA Family Discontinuation 18/Apr/2011
标准包装： 90
系列： Spartan®-IIE
LAB/CLB数： 384
逻辑元件/单元数： 1728
RAM 位总计： 32768
输入/输出数： 182
门数： 50000
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 256-LBGA
供应商设备封装： 256-FTBGA
其它名称： 122-1329
DS077-2 (v3.0) August 9, 2013
www.xilinx.com
27
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simultane-
ously. To configure multiple devices in this way, wire the indi-
vidual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
page 23.
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 16, page 23.
The timing for Slave Parallel mode is shown in Figure 26,
page 50.
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1.
Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2.
On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3.
Repeat steps 1 and 2 until all the data has been sent.
4.
Deassert CS and WRITE.
Figure 20: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
Spartan-IIE
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CS(1)
Spartan-IIE
DS077-2_06_110102
GND
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