参数资料
| 型号： | XC3020A-7PC84C |
| 厂商： | Xilinx Inc |
| 文件页数： | 21/76页 |
| 文件大小： | 0K |
| 描述： | IC LOGIC CL ARRAY 2000GAT 84PLCC |
| 产品变化通告： | Product Discontinuation 27/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 64 |
| RAM 位总计： | 14779 |
| 输入/输出数： | 64 |
| 门数： | 1500 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC |
| 其它名称： | 122-1010 |
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R
XC3000 Series Field Programmable Gate Arrays
7-30
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
Note:
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted
immediately after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
6
BUSY
T
D6
DOUT
RDY/BUSY
D7
D0
D1
D2
4
WTRB
T
Valid
2
DC
T
1
CA
T
CCLK
D0-D7
CS2
WS, CS0, CS1
3
CD
T
WRITE TO FPGA
X5992
Previous Byte
New Byte
Description
Symbol
Min
Max
Units
WRITE
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
1TCA
100
ns
DIN Setup time required
DIN Hold time required
2
3
TDC
TCD
60
0
ns
RDY/BUSY delay after end of WS
4TWTRB
60
ns
RDY
Earliest next WS after end of BUSY
5TRBWT
0ns
BUSY Low time generated
6
TBUSY
2.5
9
CCLK
periods
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
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| XC3020A-7PC84C0100 | 制造商:Xilinx 功能描述: |
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