参数资料
| 型号： | XC3020A-7PC84C |
| 厂商： | Xilinx Inc |
| 文件页数： | 33/76页 |
| 文件大小： | 0K |
| 描述： | IC LOGIC CL ARRAY 2000GAT 84PLCC |
| 产品变化通告： | Product Discontinuation 27/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 64 |
| RAM 位总计： | 14779 |
| 输入/输出数： | 64 |
| 门数： | 1500 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC |
| 其它名称： | 122-1010 |
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R
November 9, 1998 (Version 3.1)
7-41
XC3000 Series Field Programmable Gate Arrays
7
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Note:
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
XC3000A DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A.
3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
Symbol
Description
Min
Max
Units
VCC
Supply voltage relative to GND Commercial 0
°C to +85°C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40
°C to +100°C junction
4.5
5.5
V
VIHT
High-level input voltage — TTL configuration
2.0
VCC
V
VILT
Low-level input voltage — TTL configuration
0
0.8
V
VIHC
High-level input voltage — CMOS configuration
70%
100%
VCC
VILC
Low-level input voltage — CMOS configuration
0
20%
VCC
TIN
Input signal transition time
250
ns
Symbol
Description
Min
Max
Units
VOH
High-level output voltage (@ IOH = –4.0 mA, VCC min)
Commercial
3.86
V
VOL
Low-level output voltage (@ IOL = 4.0 mA, VCC min)
0.40
V
VOH
High-level output voltage (@ IOH = –4.0 mA, VCC min)
Industrial
3.76
V
VOL
Low-level output voltage (@ IOL = 4.0 mA, VCC min)
0.40
V
VCCPD
Power-down supply voltage (PWRDWN must be Low)
2.30
V
ICCPD
Power-down supply current
(VCC(MAX) @ TMAX)
3020A
3030A
3042A
3064A
3090A
100
160
240
340
500
A
ICCO
Quiescent FPGA supply current in addition to ICCPD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
500
10
A
IIL
Input Leakage Current
–10
+10
A
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
16
20
pF
IRIN
Pad pull-up (when selected) @ VIN = 0 V
3
0.02
0.17
mA
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
3.4
mA
Product Obsolete or Under Obsolescence
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