参数资料
| 型号： | XC3042A-7PQ100C |
| 厂商： | Xilinx Inc |
| 文件页数： | 34/76页 |
| 文件大小： | 0K |
| 描述： | IC LOGIC CL ARRAY 4200GAT 100PQF |
| 产品变化通告： | Product Discontinuation 27/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 144 |
| RAM 位总计： | 30784 |
| 输入/输出数： | 82 |
| 门数： | 3000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 其它名称： | 122-1026 |
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R
XC3000 Series Field Programmable Gate Arrays
7-6
November 9, 1998 (Version 3.1)
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Con-
figurable Logic Blocks (CLBs) performs user-specified logic
functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks, analo-
gous to printed circuit board traces connecting MSI/SSI
packages.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by pro-
gram-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the device at power-up and may be reloaded
on command. The FPGA includes logic and control signals
to implement automatic or passive configuration. Program
data may be either bit serial or byte parallel. The develop-
ment system generates the configuration program bit-
stream used to configure the device. The memory loading
process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory
in the Field Programmable Gate Array has been designed
specifically for high reliability and noise immunity. Integrity
of the device configuration memory based on this design is
assured even under adverse conditions. As shown in
Figure 3, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading
cell data. The cell is only written during configuration and
only read during readback. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
P9
P8
P7
P6
P5
P4
P3
P2
GND
PWR
DN
P11
P12
P13
U61
TCL
KIN
AD
AC
AB
AA
3-State Buffers With Access
to Horizontal Long Lines
Configurable Logic
Blocks
Interconnect Area
BB
BA
Frame
Pointer
Configuration Memory
I/O Blocks
X3241
Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC3042A-7PQ100C0167 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100C0262 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100C0341 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100I | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XC3042A-7PQG100I | 制造商:Xilinx 功能描述: |
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