参数资料
| 型号： | XC3042A-7PQ100C |
| 厂商： | Xilinx Inc |
| 文件页数： | 51/76页 |
| 文件大小： | 0K |
| 描述： | IC LOGIC CL ARRAY 4200GAT 100PQF |
| 产品变化通告： | Product Discontinuation 27/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB数： | 144 |
| RAM 位总计： | 30784 |
| 输入/输出数： | 82 |
| 门数： | 3000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 其它名称： | 122-1026 |
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R
November 9, 1998 (Version 3.1)
7-57
XC3000 Series Field Programmable Gate Arrays
7
XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
Speed Grade
-4-3-2-1
-09
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q)
with latch transparent(XC3100A)Clock (IK)
to Registered In (Q)
3
4
TPID
TPTG
TIKRI
2.5
12.0
2.5
2.2
11.0
2.2
2.0
11.0
1.9
1.7
10.0
1.7
1.55
9.2
1.55
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3120A, XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
1TPICK
10.6
10.7
11.0
11.2
11.6
9.4
9.5
9.7
9.9
10.3
8.9
9.0
9.2
9.4
9.8
8.0
8.1
8.3
8.5
8.9
7.2
7.3
7.5
7.7
8.1
ns
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
(XC3100A)
3-state to Pad
begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad
active and valid (fast) (XC3100A)
same
(slew -rate limited)
7
10
9
8
TOKPO
TOPF
TOPS
TTSHZ
TTSON
5.0
12.0
3.7
11.0
6.2
10.0
17.0
4.4
10.0
3.3
9.0
5.5
9.0
15.0
3.7
9.7
3.0
8.7
5.0
8.5
14.2
3.4
8.4
3.0
8.0
4.5
6.5
11.5
3.3
6.9
2.9
6.5
4.05
5.0
8.6
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
(XC3100A)
Output (O) to clock (OK) hold time
5
6
TOOK
TOKO
4.5
0
3.6
0
3.2
0
2.9
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
TIOH
TIOL
FCLK
2.0
227
1.6
270
1.3
323
1.3
323
1.3
370
ns
MHz
Global Reset Delays
RESET Pad to Registered In
(Q)
(XC3142A)
(XC3190A)
RESET Pad to output pad
(fast)
(slew-rate limited)
13
15
TRRI
TRPO
15.0
25.5
20.0
27.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
14.4
21.0
17.0
21.0
ns
Preliminary
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC3042A-7PQ100C0167 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100C0262 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100C0341 | 制造商:Xilinx 功能描述: |
| XC3042A-7PQ100I | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XC3042A-7PQG100I | 制造商:Xilinx 功能描述: |
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