参数资料
型号: XC3090L-8PC84C
厂商: Xilinx Inc
文件页数: 65/76页
文件大小: 0K
描述: IC FPGA 3.3V C-TEMP 84-PLCC
产品变化通告: XC3000(L) Discontinuation 01/Feb/2003
标准包装: 15
系列: XC3000A/L
LAB/CLB数: 320
RAM 位总计: 64160
输入/输出数: 70
门数: 6000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC
R
XC3000 Series Field Programmable Gate Arrays
7-70
November 9, 1998 (Version 3.1)
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* Indicates unconnected package pins (14) for the XC3042A.
PGA
Pin
Number
XC3042A
XC3064A
PGA
Pin
Number
XC3042A
XC3064A
PGA
Pin
Number
XC3042A
XC3064A
PGA
Pin
Number
XC3042A
XC3064A
C4
GND
B13
M1-RD
P14
RESET
M3
DOUT-I/O
A1
PWRDN
C11
GND
M11
VCC
P1
CCLK
C3
I/O-TCLKIN
A14
M0-RT
N13
DONE-PG
M4
VCC
B2
I/O
D12
VCC
M12
D7-I/O
L3
GND
B3
I/O
C13
M2-I/O
P13
XTL1-I/O-BCLKIN
M2
A0-WS-I/O
A2
I/O*
B14
HDC-I/O
N12
I/O
N1
A1-CS2-I/O
B4
I/O
C14
I/O
P12
I/O
M1
I/O
C5
I/O
E12
I/O
N11
D6-I/O
K3
I/O
A3
I/O*
D13
I/O
M10
I/O
L2
A2-I/O
A4
I/O
D14
LDC-I/O
P11
I/O*
L1
A3-I/O
B5
I/O
E13
I/O*
N10
I/O
K2
I/O
C6
I/O
F12
I/O
P10
I/O
J3
I/O
A5
I/O
E14
I/O
M9
D5-I/O
K1
A15-I/O
B6
I/O
F13
I/O
N9
CS0-I/O
J2
A4-I/O
A6
I/O
F14
I/O
P9
I/O*
J1
I/O*
B7
I/O
G13
I/O
P8
I/O*
H1
A14-I/O
C7
GND
G14
INIT-I/O
N8
D4-I/O
H2
A5-I/O
C8
VCC
G12
VCC
P7
I/O
H3
GND
A7
I/O
H12
GND
M8
VCC
G3
VCC
B8
I/O
H14
I/O
M7
GND
G2
A13-I/O
A8
I/O
H13
I/O
N7
D3-I/O
G1
A6-I/O
A9
I/O
J14
I/O
P6
CS1-I/O
F1
I/O*
B9
I/O
J13
I/O
N6
I/O*
F2
A12-I/O
C9
I/O
K14
I/O
P5
I/O*
E1
A7-I/O
A10
I/O
J12
I/O
M6
D2-I/O
F3
I/O
B10
I/O
K13
I/O
N5
I/O
E2
I/O
A11
I/O*
L14
I/O*
P4
I/O
D1
A11-I/O
C10
I/O
L13
I/O
P3
I/O
D2
A8-I/O
B11
I/O
K12
I/O
M5
D1-I/O
E3
I/O
A12
I/O*
M14
I/O
N4
RDY/BUSY-RCLK-I/O
C1
I/O
B12
I/O
N14
I/O
P2
I/O
B1
A10-I/O
A13
I/O*
M13
XTL2(IN)-I/O
N3
I/O
C2
A9-I/O
C12
I/O
L12
GND
N2
D0-DIN-I/O
D3
VCC
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