参数资料
| 型号： | XCV405E-7BG560C |
| 厂商： | Xilinx Inc |
| 文件页数： | 41/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 560-MBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 2400 |
| 逻辑元件/单元数： | 10800 |
| RAM 位总计： | 573440 |
| 输入/输出数： | 404 |
| 门数： | 129600 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 560-LBGA，金属 |
| 供应商设备封装： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
25
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Operating Modes
Virtex-E block SelectRAM+ memory supports two operating
modes.
Read Through
Write Back
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on the desire to have a faster clock-to-out
versus set-up time. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the read
pulse clock.
Write Back (one clock edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
1.
All inputs are registered with the port clock and have a
set-up to clock timing specification.
2.
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
3.
The block SelectRAM elements are true SRAM
memories and do not have a combinatorial path from
the address to the output. The LUT SelectRAM+ cells in
the CLBs are still available with this function.
4.
The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
5.
A write operation requires only one clock edge.
6.
A read operation requires only one clock edge.
The output ports are latched with a self-timed circuit to guar-
antee a glitch-free read. The state of the output port does
not change until the port executes another read or write
operation.
Library Primitives
SelectRAM+ primitives. Table 14 describes all of the avail-
able primitives for synthesis and simulation.
Figure 31: Dual-Port Block SelectRAM+ Memory
Figure 32: Single-Port Block SelectRAM+ Memory
Table 14:
Available Library Primitives
Primitive
Port A Width
Port B Width
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
1N/A
1
2
4
8
16
RAMB4_S2
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
2N/A
2
4
8
16
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
4N/A
4
8
16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
8N/A
8
16
RAMB4_S16
RAMB4_S16_S16
16
N/A
16
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
ds022_032_121399
ds022_033_121399
DO[#:0]
WE
EN
RST
CLK
ADDR[#:0]
DI[#:0]
RAMB4_S#
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| XCV405E-6BG560I | IC FPGA 1.8V 560-MBGA |
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| XCV600E-7FG900C | IC FPGA 1.8V C-TEMP 900-FBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV405E-7BG560I | 功能描述:IC FPGA 1.8V 560-MBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-E EM 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-7BG676C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG676I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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