参数资料
| 型号： | XCV812E-8FG900C |
| 厂商： | Xilinx Inc |
| 文件页数： | 28/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 900-FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 4704 |
| 逻辑元件/单元数： | 21168 |
| RAM 位总计： | 1146880 |
| 输入/输出数： | 556 |
| 门数： | 254016 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 900-BBGA |
| 供应商设备封装： | 900-FBGA |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
13
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Table 9 lists the total number of bits required to configure
each device.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
For more detailed information on serial PROMs see the
PROM data sheet at ds026.pdf.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13 shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected. However, it is recommended to drive the con-
figuration
mode
pins
externally.
shows
slave-serial mode programming switching characteristics.
Table 10 provides more detail about the characteristics
shown in Figure 14. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Boundary-scan mode
0
1
N/A
1
No
Yes
SelectMAP mode
0
1
0
In
8
No
Yes
Slave-serial mode
0
1
In
1
Yes
Table 8:
Configuration Codes
Configuration Mode
M2
M1
M0
CCLK Direction
Data Width
Serial Dout
Configuration Pull-ups
Table 9:
Virtex-E Bitstream Lengths
Device
# of Configuration Bits
XCV405E
3,430,400
XCV812E
6,519,648
Table 10:
Master/Slave Serial Mode Programming Switching
Description
Figure
References
Symbol
Values
Units
CCLK
DIN setup/hold, slave mode
1/2
TDCC/TCCD
5.0/0.0
ns, min
DIN setup/hold, master mode
1/2
TDSCK/TCKDS
5.0/0.0
ns, min
DOUT
3TCCO
12.0
ns, max
High time
4TCCH
5.0
ns, min
Low time
5TCCL
5.0
ns, min
Maximum Frequency
FCC
66
MHz, max
Frequency Tolerance, master mode with respect to nominal
+45% –30%
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV812E-8FG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCVR-040L31 | 制造商:WWP 功能描述: |
| XCW 10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM; Drill Bit Size Metric:10mm; Overall Length:30.5mm; SVHC:No SVHC (19-Dec-2012); Countersink Angle:90; Drill Bit Type:Countersink; Drill Point Diameter:10mm; External Diameter:10mm; Head Diameter:10mm; ;RoHS Compliant: NA |
| XCW10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
| XCW15 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
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