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参数资料
型号： XE8000EV104
厂商： Semtech
文件页数： 10/156页
文件大小： 0K
描述： EVAL BOARD FOR XE8805AMI028LF
标准包装： 1
类型： MCU
适用于相关产品： XE88LC05AMI028
所含物品： 完全组装的评估板
Semtech 2006
www.semtech.com
16-21
XE8805/05A
Specifications (Cont’d)
VALUE
PARAMETER
MIN
TYP
MAX
UNITS
COMMENTS/CONDITIONS
POWER SUPPLY
Voltage Supply Range, VDD
Analog
Quiescent
Current
Consumption, Total (IQ)
ADC Only
PGA1
PGA2
PGA3
Analog Power Dissipation
Normal Power Mode
3/4 Power Reduction Mode
1/2 Power Reduction Mode
1/4 Power Reduction Mode
+2.4
+5
720/620
250/190
165/150
130/120
175/160
3.6/1.9
2.7/1.4
1.8/0.9
0.9/0.5
+5.5
V
A
mW
Only Acquisition Chain
VDD = 5V/3V
All PGAs & ADC Active
VDD = 5V/3V (Note 16)
VDD = 5V/3V (Note 17)
VDD = 5V/3V (Note 18)
VDD = 5V/3V (Note 19)
TEMPERATURE
Specified Range
Operating Range
-40
+85
+125
°C
Notes:
(1)
Gain
defined
as
overall
PGA
gain
GDTOT
=
GD1GD2GD3.
Maximum
input
voltage
is
given
by:
VIN,MAX = ±(VREF/2)(OSR/OSR+1).
(2)
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
(3)
Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
512kHz. This figure must be multiplied by 2 for fS = 256kHz, 4 for fS = 128kHz. Input impedance is proportional to 1/fS.
(4)
Figure
independent
from
PGA1
gain
and
sampling
frequency
fS.
See
model
of
Figure
16-18(a).
See equation Eq. 21 to calculate equivalent input noise.
(5)
Figure independent on PGA2 gain and sampling frequency fS. See model of Figure 16-18(a). See equation Eq. 21 to calculate
equivalent input noise.
(6)
Figure independent on PGA3 gain and sampling frequency fS. See model of Figure 16-18(a) and equation Eq. 21 to calculate
equivalent input noise.
(7)
Resolution is given by n = 2
log2(OSR) + log2(N
ELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to
1, 2, 4 or 8.
(8)
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
(9)
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed). (See Figure 16-19)
(10) Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For
± 1 LSB offset, N
ELCONV must be ≥2.
(11) INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale.
(12) DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
(13) Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
(14) Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can
be set to 1, 2, 4 or 8.
(15) PGAs are reset after each writing operation to registers RegAcCfg1-5. The ADC must be started after a PGA or inputs common-
mode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching.
Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of
cycles. This delay does not apply to conversions made without the PGAs.
(16) Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = ‘11’ and IB_AMP_ADC[1:0] = ‘11’.
(17) Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’.
(18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’.
(19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’.
16.8.3
Linearity
16.8.3.1
Integral non-linearity
The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all
PGA stages bypassed) is shown in Figure 16-8.
Not
Recommended
for
New
Designs
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