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参数资料
型号： XE8000EV104
厂商： Semtech
文件页数： 56/156页
文件大小： 0K
描述： EVAL BOARD FOR XE8805AMI028LF
标准包装： 1
类型： MCU
适用于相关产品： XE88LC05AMI028
所含物品： 完全组装的评估板
Semtech 2006
www.semtech.com
20-9
XE8805/05A
The duty cycle ratio DCR of the PWM signal is defined as:
Tper
Th
DCR
=
DCR can be selected between 0 % and
100
*
2
1
2
resolution
%.
DCR in % in function of the RegCntX content(s) is given by the relation:
resolution
DCR
2
RegCntX
*
100
=
20.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 20-14 shows the capture condition as a function of the setting of these
configuration bits.
CapSel(1:0)
Selected capture signal
CapFunc
Selected condition
Capture condition
11
1 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
1 K rising edge
1 K falling edge
1 K both edges
10
32 K
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
32 K rising edge
32 K falling edge
32 K both edges
01
PA3
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA3 rising edge
PA3 falling edge
PA3 both edges
00
PA2
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
-
PA2 rising edge
PA2 falling edge
PA2 both edges
Table 20-14: Capture condition selection
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
Not
Recommended
for
New
Designs
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