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参数资料
型号： XE8000EV104
厂商： Semtech
文件页数： 53/156页
文件大小： 0K
描述： EVAL BOARD FOR XE8805AMI028LF
标准包装： 1
类型： MCU
适用于相关产品： XE88LC05AMI028
所含物品： 完全组装的评估板
Semtech 2006
www.semtech.com
20-6
XE8805/05A
CascadeAB
CountPWM0
CapFunc(1:0)
Counter A
mode
Counter B
mode
IrqA
source
IrqB
source
PB(0)
function
0
00
Counter 8b
Downup: A
Counter 8b
Downup: B
Counter
A
Counter
B
PB(0)
1
0
00
Counter 16b AB
Downup: A
Counter
AB
-
PB(0)
0
1
00
PWM 8b
Down
Counter 8b
Down
-
Counter
B
PWM A
1
00
PWM 10 – 16b AB
Down
-
PWM AB
0
1x
or
x1
Captured
counter 8b
Downup: A
Captured
counter 8b
Downup: B
Capture
A
Capture
B
PB(0)
1
0
1x
or
x1
Captured counter 16b AB
Downup: A
Capture
AB
Capture
AB
PB(0)
0
1
1x
or
x1
PWM 8b
Down
Captured
counter 8b
Downup: B
Must not
be used
Capture
B
PWM A
Table 20-11: Operating modes of the counters A and B
Table 20-12 shows the different operation modes of the counters C and D as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit
CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
CascadeCD
CountPWM1
Counter C
mode
Counter D
mode
IrqC
Source
IrqD
source
PB(1)
function
0
Counter 8b
Downup: C
Counter 8b
Downup: D
Counter
C
Counter
D
PB(1)
1
0
Counter 16b CD
Downup: C
Counter
CD
-
PB(1)
0
1
PWM 8b
Down
Counter 8b
Down
-
Counter
D
PWM C
1
PWM 10 – 16b CD
Down
-
PWM CD
Table 20-12: Operating modes of the counters C and D
20.9
Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods applied on the counter clock input.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for the counters A and C.
Not
Recommended
for
New
Designs
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