参数资料
型号: XE8805AMI028LF
厂商: Semtech
文件页数: 9/156页
文件大小: 0K
描述: IC DAS 16BIT FLASH 8K MTP 64LQFP
标准包装: 160
系列: XE880x
应用: 感测机
核心处理器: Coolrisc816?
程序存储器类型: 闪存(22 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
输入/输出数: 24
电源电压: 2.4 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
包装: 托盘
供应商设备封装: 64-LQFP(10x10)
产品目录页面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2006
www.semtech.com
16-20
XE8805/05A
16.8.2
Specifications
Unless otherwise specified: Temperature TA = +25°C, VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling
frequency fS = 500kHz, Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] =
IB_AMP_PGA[1:0]
= '11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
VALUE
PARAMETER
MIN
TYP
MAX
UNITS
COMMENTS/CONDITIONS
ANALOG
INPUT
CHARACTERISTICS
Differential Input Voltage Ranges
VIN = (VINP - VINN)
Reference Voltage Range
VREF = (VREFP – VREFN)
-2.42
-24.2
-2.42
+2.42
+24.2
+2.42
VDD
V
mV
V
Gain = 1, OSR = 32 (Note 1)
Gain = 100, OSR = 32
Gain = 1000, OSR = 32
PROGRAMMABLE
GAIN
AMPLIFIERS (PGA)
Total PGA Gain, GDTOT
PGA1 Gain, GD1
PGA2 Gain, GD2
PGA3 Gain, GD3
Gain Setting Precision (each stage)
Gain Temperature Dependence
Offset
PGA2 Offset, GDoff2
PGA3 Offset, GDoff3
Offset Setting Precision (PGA2 or 3)
Offset Temperature Dependence
Input Impedance
PGA1
PGA2, PGA3
Output RMS Noise
PGA1
PGA2
PGA3
0.5
1
0
-3
-1
-127/12
-3
1500
150
±0.5
±5
±0.5
±5
205
340
365
1000
10
127/12
+3
+1
+127/12
+3
V/V
%
ppm/°C
V/V
%
ppm/°C
k
k
k
V
See Table 16-14
See Table 16-15
Step=1/12
V/V,
See
Table
16-17
Step=0.2 V/V, See Table 16-16
Step=1/12
V/V,
See
Table
16-18
(Note 2)
PGA1 Gain = 1 (Note 3)
PGA1 Gain = 10 (Note 3)
Maximal gain (Note 3)
(Note 4)
(Note 5)
(Note 6)
ADC STATIC PERFORMANCE
Resolution, n
No Missing Codes
Gain Error
Offset Error
Integral Non-Linearity, INL
Resolution n = 16 Bits
Differential Non-Linearity, DNL
Resolution n = 16 Bits
Power Supply Rejection Ratio, PSRR
6
±0.15
±1
±1.0
±0.5
78
72
16
Bits
% of FS
LSB
dB
(Note 7)
(Note 8)
(Note 9)
n = 16 bits (Note 10)
(Note 11)
(Note 12)
VDD = 5V ± 0.3V (Note 13)
VDD = 3V ± 0.3V (Note 13)
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Conversion Time, TCONV
Throughput Rate (Continuous Mode),
1/TCONV
Nbr of Initialization Cycles, NINIT
Nbr of End Conversion Cycles, NEND
PGA Stabilization Delay
3
0
133
1027
3.76
0.49
OSR
2
5
kHz
cycles/fS
kSps
cycles
n = 12 bits (Note 14)
n = 16 bits (Note 14)
n = 12 bits, fS = 500kHz
n = 16 bits, fS = 500kHz
(Note 15)
DIGITAL OUTPUT
ADC Output Data Coding
Binary Two’s Complement
See Table 16-24 and Table
16-25
Not
Recommended
for
New
Designs
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