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参数资料
| 型号： | XR16V794IV-0B-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 21/53页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16V794-B 64TQFP |
| 设计资源： | XR17V798/794 Eval Board Schematic |
| 标准包装： | 1 |
| 系列： | * |
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XR16V794
28
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16V794. They are present for 16C550 compat-
ibility during Internal loopback, see
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read Only
4.2
Transmit Holding Register (THR) - Write Only
.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 3:0 enables the XR16V794 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO mode).
B.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty.
E.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
1 0 1 0
TXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1
RXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1
RXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 0
XCHAR
R
0
TX Xon
Indicator
TX Xoff
Indicator
Xon Det.
Indicator
Xoff Det.
Indicator
Self clear
after read
1 1 0 0
XOFF1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 1
XOFF2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 0
XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 1
XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
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相关代理商/技术参数 |
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| XR16V794IV-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V798 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL |
| XR16V798_08 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL |
| XR16V798IQ | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL |
| XR16V798IQ-0A-EVB | 功能描述:UART 接口集成电路 Supports V798 100 ld QFP,ISA Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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