参数资料
型号: XR16V794IV-0B-EVB
厂商: Exar Corporation
文件页数: 26/53页
文件大小: 0K
描述: EVAL BOARD FOR XR16V794-B 64TQFP
设计资源: XR17V798/794 Eval Board Schematic
标准包装: 1
系列: *
XR16V794
32
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM, DLD) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER
TABLE
FCTR
BIT-7
FCTR
BIT-6
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
Table-A
0
1
0
1
0
1
0
1 (default)
4
8
14
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580, 16L580
Table-B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
24
28
16
8
24
30
16C650A, 16L651
Table-C
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
16C654
Table-D
1
X
Programmable
via RXTRG
register
Programmable
via TXTRG
register
16L2752, 16L2750,
16C2852, 16C850,
16C854, 16C864
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