参数资料
型号: XR16V794IV-0B-EVB
厂商: Exar Corporation
文件页数: 31/53页
文件大小: 0K
描述: EVAL BOARD FOR XR16V794-B 64TQFP
设计资源: XR17V798/794 Eval Board Schematic
标准包装: 1
系列: *
XR16V794
37
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
4.10
Modem Status Register (MSR) - Write Only
The upper four bits 7:4 of this register set the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks. Table 16 shows the selection. The bits are enabled by EFR bit-4.
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
DELAY IN DATA BIT(S) TIME
0
1
0
1
0
2
0
1
3
0
1
0
4
9
1
0
1
5
0
1
0
6
0
1
7
1
0
8
1
0
1
9
1
0
1
0
10
1
0
1
11
1
0
12
1
0
1
13
1
0
14
1
15
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