
á
á THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER XRT72L53
PRELIMINARY
REV. P1.1.7
240
Setting this bit-field to “1” enables the Receive Sec-
tion (at the Block Level) for interrupt generation. Con-
versely, setting this bit-field to “0” disables the Re-
ceive Section for interrupt generation.
4.3.6.2
Enabling/Disabling and Servicing
Receive Section Interrupts
As mentioned earlier, the Receive Section of the
XRT72L53 Framer IC contains numerous interrupts.
The Enabling/Disabling and Servicing of each of
these interrupts is described below.
4.3.6.2.1
The Change of State on Receive LOS
Interrupt
If the Change of State on Receive LOS (Loss of Sig-
nal) Interrupt is enabled, then the XRT72L53 Framer
IC will generate an interrupt in response to either of
the following conditions.
1. When the XRT72L53 Framer IC declares an LOS
(Loss of Signal) condition, and
2. When the XRT72L53 Framer IC clears the LOS
(Loss of Signal) condition.
Conditions causing the XRT72L53 Framer IC to
declare an LOS condition
If the XRT7300 LIU IC declares an LOS condition,
and drives the RLOS input pin (of the XRT72L53
Framer IC) "High".
If the XRT72L53 Framer IC detects a 180 consecu-
tive “0’s”, via the RxPOS and RxNEG input pins.
Conditions causing the XRT72L53 Framer IC to
clear the LOS condition.
When the XRT7300 LIU IC ceases declaring an
LOS condition and drives the RLOS input pin (of
the XRT72L53 Framer IC) "Low".
When the XRT72L53 Framer IC detects at least 60
marks (via the RxPOS and RxNEG input pins) out
of 180 bit-periods.
Enabling and Disabling the Change of State on
Receive LOS Interrupt:
The user can enable or disable the Change of State
on Receive LOS Interrupt, by writing the appropriate
value into Bit 6 (LOS Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Change of State on Receive LOS In-
terrupt
Whenever the XRT72L53 Framer IC detects this in-
terrupt, it will do all of the following.
It will assert the Interrupt Request output pin (INT)
by driving this pin "Low".
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
RxDS3/E3
Interrupt
Enable
Not Used
TxDS3/E3
Interrupt
Enable
One Second
Interrupt
Enable
R/W
RORO
RO
RORO
R/W
X
0000
000
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
0
0000
000