参数资料
型号: XRT73LC03AIV-F
厂商: Exar Corporation
文件页数: 24/61页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 120LQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 3/3
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 120-LQFP
供应商设备封装: 120-LQFP(14x20)
包装: 托盘
XRT73LC03A
28
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.4
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 15. The
Transmit Section (of a Channel) typically samples the
data on the TPData_(n) and TNData_(n) input pins on
the falling edge of TxClk_(n).
TxClk_(n) is the clock signal that is of the selected
data rate frequency, E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Sec-
tion samples a "1" on the TPData_(n) input pin, then
the Transmit Section of the device ultimately gener-
ates a positive polarity pulse via the TTIP_(n) and
TRing_(n) output pins across a 1:1 transformer. If the
Transmit Section samples a "1" on the TNData_(n) in-
put pin, then the Transmit Section of the device ulti-
mately generates a negative polarity pulse via the
TTIP_(n) and TRing_(n) output pins across a 1:1
transformer.
2.1.2
Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73LC03A in the
HOST Mode.
Write a "1" into the TxBin_(n) (TRANSMIT BINary)
bit-field of Command Register CR1-(n) shown below.
NOTE: Please refer to Table 2 for the Address of the indi-
vidual Channel(n).
The Transmit Section of each channel samples this
input pin on the falling edge of the TxClk_(n) clock
signal and encodes this data into the appropriate bi-
polar line signal across the TTIP_(n) and TRing_(n)
output pins.
NOTES:
FIGURE 14. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FOR-
MAT FROM THE
TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL
Exar E3/DS3/STS-1 LIU
Transmit
Logic
Block
TxPOS
TxNEG
TxLineClk
TPData
TNData
TxClk
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
FIGURE 15. THE XRT73LC03A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
TxClk
TPData
TNData
Data
1
0
COMMAND REGISTER CR1-(n)
D4
D3
D2
D1
D0
TxOFF_(n)
TAOS_(n)
TxClkINV_(n)
TxLEV_(n)
TxBin_(n)
XX
X
1
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