参数资料
| 型号： | XRT73LC03AIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 47/61页 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 3/3 |
| 规程： | DS3，E3，STS-1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-LQFP（14x20） |
| 包装： | 托盘 |
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XRT73LC03A
49
REV. 1.0.4
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, pull both the LLB input pin and
the RLB input pin "High".
4.3
THE REMOTE LOOP-BACK MODE
When a given channel is configured to operate in the
Remote Loop-Back Mode, the channel ignores any
signals that are input to the TPData and TNData input
pins. The channel receives the incoming line signal
via the RTIP and RRing input pins. This data is pro-
cessed through the entire Receive Section and is out-
put to the Receive Terminal Equipment via the RPOS,
RNEG and RxClk output pins. Additionally, this data
is also internally looped back into the Pulse-Shaping
block within the Transmit Section. At this point, this
data is routed through the remainder of the Transmit
Section of the channel and transmitted out onto the
line via the TTIP_(n) and TRing_(n) output pins.
Figure 35 illustrates the path that the data takes when
the chip is configured to operate in the Remote Loop-
Back Mode.
Configure a channel to operate in the Remote Loop-
Back Mode by employing either one of the following
two steps
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Remote
Loop-Back Mode, write a "1" into the RLB bit-field,
and a "0" into the LLB bit-field, within Command Reg-
ister CR4.
b. Operating in the Hardware Mode
To configure Channel(n) to operate in the Remote
Loop-Back Mode, pull both the RLB_(n) input pin to
“High" and the LLB_(n) input pin to "Low".
FIGURE 35. THE REMOTE LOOP-BACK PATH, WITHIN A GIVEN CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
XSTS-1/DS3_(n)
E3_(n)
LLB_(n)
RLB_(n)
XX
X
0
1
相关PDF资料 |
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| XRT73LC04AIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT73LC04A | 制造商:EXAR 制造商全称:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04A_08 | 制造商:EXAR 制造商全称:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AES | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT73LC04AIV | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT73LC04AIV-F | 功能描述:外围驱动器与原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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